View M69KB096AA85AW8_307715.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M69KB096AA
64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM
FEATURES SUMMARY

SUPPLY VOLTAGE - VCC = 1.7 to 1.95V core supply voltage - VCCQ = 1.7 to 3.3V for I/O buffers ASYNCHRONOUS MODES - Asynchronous Random Read: 70ns and 85ns access time - Asynchronous Write - Asynchronous Page Read Page Size: 16 words Subsequent read within page: 20ns SYNCHRONOUS BURST READ AND WRITE MODES - Burst Write in Continuous Mode - Burst Read: Fixed Length (4, 8, or 16 Words) or Continuous mde Maximum Clock Frequency: 66MHz, 80MHz Burst initial latency: 50ns (4 clock cycles) at 80MHz Output delay: 9ns at 80MHz BYTE CONTROL BY LB/UB LOW POWER CONSUMPTION - Asynchronous Random Read Mode: < 25mA - Asynchronus Page Read Mode (subsequent read operations): < 15mA - Synchronous Burst Read Initial access: < 35mA Continuous Burst Read: < 15mA - Standby Current: 120A - Deep Power-Down Current: 10A (typ)
Figure 1. Package
Wafer
LOW POWER FEATURES - Temperature Compensated Refresh (TCR) - Partial Array Refresh (PAR) - Deep Power-Down (DPD) Mode OPERATING TEMPERATURE - -30C to +85C
THE M69KB096AA IS ONLY AVAILABLE AS PART OF A MULTI-CHIP PACKAGE PRODUCT
January 2006
1/48
M69KB096AA
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Clock Input (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VCCQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Asynchronous Random Read and Write Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Asynchronous Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Synchronous Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Deep Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Programming and Reading the Configuration Registers using the CR Controlled Method . 13 Programming and Reading the Configuration Registers by the Software Method. . . . . . . . . 13 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Mode Bit (BCR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Configuration Bit (BCR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Driver Strength Bit (BCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/48
M69KB096AA
Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Page Mode Operation Bit (RCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Temperature Compensated Refresh Bits (RCR6-RCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/48
M69KB096AA
SUMMARY DESCRIPTION
The M69KB096AA is a 64 Mbit (67,108,864 bit) PSRAM, organized as 4,194,304 words by 16 bits. The memory array is implemented using a one transistor-per-cell topology, to achieve bigger array sizes. This device is a high-speed CMOS, dynamic random-access memory. It provides a high-density solution for low-power handheld applications. The M69KB096AA includes the industry standard Flash memory burst mode that dramatically increases read/write over that of other low-power SRAM or PSRAMs. The PSRAM interface supports both asynchronous and burst-mode transfers. Page mode accesses are also included as a bandwidthenhancing extension to the asynchronous read protocol. PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory controller, and has no significant impact on the device read/write performance. The device has two configuration registers, accessible to the user to define the device operation: the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR). The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. Overall, it is identical to its counterpart in burst-mode Flash memory devices. The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At power-up, these registers are automatically loaded with default settings and can be updated any time during normal operation. To minimize the value of the standby current during self-refresh operations, the M69KB096AA includes three system-accessible mechanisms configured via the Refresh Configuration Register (RCR): The Temperature Compensated Refresh (TCR) is used to adjust the refresh rate according to the operating temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. The Partial Array Refresh (PAR) performs a limited refresh of the part of the PSRAM array that contains essential data. The Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no essential data is being held in the device. Figure 2. Logic Diagram
VCC VCCQ
22 A0-A21 W E CR G UB LB K L M69KB096AA
16 DQ0-DQ15
WAIT
VSS
VSSQ
AI10584b
Table 1. Signal Names
A0-A21 DQ0-DQ15 E CR G W UB LB K L WAIT VCC VCCQ VSS VSSQ Address Inputs Data Inputs/Outputs Chip Enable Input Configuration Register Enable Input Output Enable Input Write Enable Input Upper Byte Enable Input Lower Byte Enable Input Clock Input Latch Enable Input Wait Output Core Supply Voltage Input/Output Buffers Supply Voltage Ground Input/Output Buffers Ground
4/48
M69KB096AA
SIGNAL DESCRIPTIONS
The signals are summarized in Figure 2., Logic Diagram, and Table 1., Signal Names. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. When disabled, the Data Inputs/Outputs are high impedance. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E). Chip Enable, E, activates the device when driven Low (asserted). When deasserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep Power-down mode. Output Enable (G). Output Enable, G, provides a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common I/O data bus. Write Enable (W). Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LB and UB are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as E remains Low. Clock Input (K). The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus frequency during Synchronous Burst Read and Write operations. The Clock input is required during all synchronous operations, except in Standby and Deep PowerDown. It must be kept Low during asynchronous operations. Configuration Register Enable (CR). When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). Latch Enable (L). The Latch Enable input is used to latch the address. Once the first address has been latched, the state of L controls whether subsequent addresses come from the address lines (L = VIL) or from the internal Burst counter (L = VIH). The Latch Enable signal, L, must be held Low, VIL, during Asynchronous operations. Wait (WAIT). The WAIT output signal provides data-valid feedback during Synchronous Burst Read and Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause data corruption. Once a Read or Write operation has been initiated, the WAIT signal goes active to indicate that the M69KB096AA device requires additional time before data can be transferred. The WAIT signal also is used for arbitration when a Read or Write operation is launched while an onchip refresh is in progress (see Figure 6., Collision Between Refresh and Read Operation and Figure 7., Collision between Refresh and Write Operation). The WAIT signal on the M69KB096AA device is typically connected to a shared system-level WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. See the Operating Modes section for details on the WAIT signal operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. VCCQ Supply Voltage. VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered independently from the core power supply, VCC. VSS Ground. The VSS Ground is the reference for all voltage measurements. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be connected to VSS.
5/48
M69KB096AA
Figure 3. Block Diagram
A21-A0 Address Decode Logic 4,096K x 16 I/O Buffers MEMORY ARRAY Refresh Configuration Register (RCR)
DQ7-DQ0
DQ15-DQ7
Bus Configuration Register (BCR)
E W G K L CR WAIT LB UB Control Logic
AI08721c
Note: Functional block diagram illustrates simplified device operation.
6/48
M69KB096AA
Table 2. Bus Modes- Asynchronous Mode
MODE Asynchronous Read Asynchronous Write Standby Write Configuration Register Deep PowerDown (DPD) POWER Active > Standby Active > Standby Standby Active Deep PowerDown K L L L L L L L X L E L L H L G L X X H W H L X L CR L L L H LB, UB L1 L1 X X WAIT
(2)
DQ15-DQ0
(1)
NOTES 3 3 4,5
Low Z Low Z High Z Low Z
Data-Out Data-In High-Z High-Z
L
X
H
X
X
X
X
High-Z
High-Z
6
Table 3. Bus Modes- Synchronous Burst Mode
MODE Initial Burst Read Initial Burst Write Subsequent Burst Operation Burst Suspend Write Configuration Register Deep PowerDown (DPD) POWER Active > Standby Active > Standby Active > Standby Active > Standby Active Deep PowerDown K L L L E L L G X H W H L CR L L LB, UB L X WAIT
(2)
DQ15-DQ0
(1)
NOTES 3, 7, 8 3, 7, 8
! ! !
X(9)
Low Z Low Z
Data-Out Data-In Data-In or Data-Out High-Z
H
L
X
X
X
L
Low Z
3, 7, 8
X
L
H
X
L
X
Low Z
3, 7
!
L
L
L
H
L
H
X
Low Z
High-Z
7, 8
X
H
X
X
X
X
High-Z
High-Z
6
Note: 1. When LB and UB are in select mode (Low), DQ15-DQ0 are affected. When only LB is in select mode, DQ7-DQ0 are affected. When only UB is in the select mode, DQ15-DQ8 are affected. 2. The WAIT polarity is configured through the Bus Configuration Register (BCR10). 3. The device consumes active power in this mode whenever addresses are changed. 4. When the device is in Standby mode, Address inputs and Data inputs/outputs are internally isolated from any external influence. 5. VIN = VCC or 0V. 6. The device remains in Deep Power-Down mode until the RCR register is reconfigured. 7. The Synchronous Burst mode is initialized through the Bus Configuration Register (BCR15). 8. The clock polarity is configured through the Bus Configuration Register (BCR6). 9. The Clock signal, K, must remain stable during Burst Suspend operations.
7/48
M69KB096AA
OPERATING MODES
The M69KB096AA supports Asynchronous Random Read, Page Read and Synchronous Burst Read and Write modes. The device mode is defined by the value that has been loaded into the Bus Configuration Register. The Page mode is controlled by the Refresh Configuration Register (RCR7). Power-Up PSRAM devices include an on-chip voltage sensor used to launch the power-up sequence. VCC and VCCQ must be applied simultaneously. Once they reach a stable level, equal to or higher than 1.70V, the device will require tVCHEL to complete its self-initialization process. During the initialization period, the E signal should remain High. Once initialization has completed, the device is ready for normal operation. Initialization will configure the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) with their default settings (see Table 5., page 16, and Table 9., Refresh Configuration Register Definition). See Figure 34., Power-Up AC Waveforms and Table 19., Power-Up AC Characteristics, for details on the Power-up timing. Asynchronous Random Read and Write Modes At power-up, the device is in Asynchronous Random Read mode. This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are initiated by bringing E, G, and LB, UB Low, VIL, while keeping W High, VIH. Valid data will be gated through the output buffers after the specific access time tAVQV has elapsed. The WAIT signal will remain active until valid data is output from the device and its state should be ignored. Write operations occur when E, W, LB and UB are driven Low. During Asynchronous Random Write operations, the G signal is "don't care" and W will override G. The data to be written is latched on the rising edge of E, W, LB or UB (whichever occurs first). During Write operations, the WAIT signal indicates to the system memory controller that data have been programmed into the memory. During asynchronous operations (Page mode disabled), the L input can either be used to latch the address or kept Low, VIL, during the entire Read/ Write operation. The Clock input signal K must be held Low, VIL. See Figures 15, 16 and Table 15. for details of Asynchronous Read AC timing requirements. See Figures 23, 24, 25, 26, and Table 17. for details of Asynchronous Write AC timing requirements. Asynchronous Page Read Mode The Asynchronous Page read mode gives greater performance, even than the traditional Asynchronous Random Read mode. The page mode is not available for write operations. Asynchronous Page Read mode is enabled by setting RCR7 to `1'. L must be driven Low, VIL, during all Asynchronous Page Read operations. In Asynchronous Page Read mode, a Page of data is internally read. Each memory page consists of 16 Words, and has the same set of values on A4-A21; only of A0 to A3 differ. The first read operation within the Page has the normal access time (tAVQV), subsequent reads within the same Page have much shorter access times (tAVQV1). If the Page changes then the normal, longer timings apply again. During Asynchronous Page Read mode, the K input must be held Low, VIL. E must be kept Low, VIL upon completion of an Asynchronous Page Read operation. The WAIT signal remains active until valid data is output from the device. See Figure 17. and Table 15. for details of the Asynchronous Page Read timing requirements. Synchronous Burst Mode Burst mode allows high-speed synchronous read and write operations. In Synchronous Burst mode, the data is input or output to or from the memory array in bursts that are synchronized with the clock. After E goes Low, the data address is latched on the first rising edge of the Clock, K. During this first clock rising edge, the W signal indicates whether the operation is going to be a Read (W=VIH, Figure 4.) or Write (W=VIL, Figure 5.). In Synchronous Burst mode, the number of Words to be input or output during a Synchronous Burst operation can be configured in the Bus Configuration Register, BCR, as fixed length (4 Words, 8 Words or 16 Words) or Continuous. In Synchronous Continuous Burst mode, the entire memory can be accessed sequentially in one Burst operation. The Latency Counter, stored in the BCR11 to BCR13 bits of the BCR register, defines how many clock cycles elapse before the first data value is transferred between the processor and the M69KB096AA. The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will be deasserted to indicate when data is to be transferred into (or out of) the memory array. The WAIT signal is also asserted when a Continuous Burst Read or Write operation crosses a row boundary. The WAIT assertion allows time for the new row to
8/48
M69KB096AA
be accessed. It also allows any pending refresh operations to be performed (see Figure 22., Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)). The processor can access other devices without being submitted to the initial burst latency by suspending the burst operation. Burst operations can be suspended by halting the Clock signal, holding it High or Low. If another device needs to use the data bus while Burst operations are suspended, the Output Enable signal, G, should be driven High, VIH, to disable data outputs; otherwise, G can remain Low, VIL. The WAIT output will remain asserted to prevent any other devices from using the processor WAIT line. Burst operations can be resumed by taking G Low, VIL, and then restarting the Clock as soon as valid data are available on the bus (see Figure 21., Synchronous Burst Read Suspend and Resume Waveforms). Mixed Mode When the BCR register is configured for synchronous operation, the device can support a combination of Synchronous Burst Read and Asynchronous Random Write operations. The Asynchronous Random Write operation requires that the Clock signal remains Low, VIL, during the entire sequence. The L signal can either be used to latch the target address or remain Low, VIL, during the entire Write operation. E must return Low, VIL, during Asynchronous and Burst operations. Note that the time, necessary to assure adequate refresh, is the same value as that for Asynchronous Read and Write mode. Mixed-mode operation greatly simplifies the interfacing with traditional burst-mode Flash Memory Controllers. Low-Power Modes Standby Mode. During Standby, the device current consumption is reduced to the level necessary to perform the memory array refresh operation. Standby operation occurs when E is High, VIH, and no transaction is in progress. The device will enter Standby mode when a Read or Write operation is completed, or when the address and control inputs remain stable for an extended period of time. This "active" Standby mode will continue until address or control inputs change. Temperature Compensated Refresh. The Temperature Compensated Refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. The leakage current of DRAM capacitive storage elements increases with the temperature. PSRAM devices, based on a DRAM architecture, consequently require increasingly frequent refresh operations to maintain data integrity as the temperature increases. At lower temperatures, the refresh rate can be decreased to minimize the standby current. The TCR mechanism allows adequate refresh rates to be set at four different temperature thresholds. These are defined by setting the RCR5 and RCR6 bits of the Refresh Configuration Register, RCR. To minimize the self refresh current consumption, the selected setting must be higher than the operating temperature of the PSRAM device. As an example, if the operating temperature is +50C, the +70C setting must be selected; the +15C and +45C settings would result in inadequate refreshing and could cause data corruption. See Table 9. for the definition of the Refresh Configuration Register bits. Partial Array Refresh. The Partial Array Refresh (PAR) performs a limited refresh of part of the PSRAM array. This mechanism enables the device to reduce the standby current by refreshing only the part of the memory array that contains essential data. Different refresh options can be defined by setting the RCR0 to RCR2 bits of the RCR Register: Full array One half of the array One quarter of the array One eighth of the array None of the array. These memory areas can be located either at the top or bottom of the memory array. The WAIT signal is used for arbitration when a read/write operation is launched while an on-chip refresh is in progress. If locations are addressed while they are undergoing refresh, the WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see Figure 6. and Figure 7., Collision between Refresh and Read or Write Operations). When the refresh operation is completed, the Read or Write operation will be allowed to continue normally.
9/48
M69KB096AA
Deep Power-Down Mode. Deep power-down (DPD) mode is used by the system memory controller to de-activate the PSRAM device when its storage capabilities are not needed. All refresh-related operations are then disabled. When the Deep Power-Down mode is enabled, the data stored in the device become corrupted. When reFigure 4. Synchronous Burst Read Mode
K Address Valid
fresh operations have been re-enabled, the device will be available for normal operations after tVCHEL (time to perform an initialization sequence). During this delay, the current consumption will be higher than the specified standby levels, but considerably lower than the active current.
A0-A21
ADV Latency Code 2 (3 clocks) E
G
W Hi Z Hi Z
WAIT
DQ0-DQ15
DQ0
DQ1
DQ2
DQ3
LB/UB Burst Read Identified (W = High)
AI06774b
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
10/48
M69KB096AA
Figure 5. Synchronous Burst Write Mode (4-word burst)
K Address Valid
A0-A21
L
E G
W
LB/UB Hi Z Hi Z
WAIT
DQ0-DQ15 Additional WAIT states inserted to allow Refresh completion
DQ0
DQ1
DQ2
DQ3
AI06776c
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
Figure 6. Collision Between Refresh and Read Operation
K Address Valid
A0-A21
L
E G
W
LB/UB Hi Z Hi Z
WAIT
DQ0-DQ15 Additional WAIT states inserted to allow Refresh completion
DQ0
DQ1
DQ2
DQ3
AI06776b
Note: Additional Wait states inserted to allow Refresh completion. Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
11/48
M69KB096AA
Figure 7. Collision between Refresh and Write Operation
K
A0-A21
Address Valid
L
E
G W
LB/UB Hi Z Hi Z
WAIT
DQ0-DQ15 Additional WAIT states inserted to allow Refresh completion
DQ0
DQ1
DQ2
DQ3
AI06777
Note: Additional Wait states inserted to allow Refresh completion. Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
12/48
M69KB096AA
CONFIGURATION REGISTERS
Two write-only user-accessible configuration registers have been included to define device operation. These registers are automatically loaded with default settings during power-up, and can be updated any time the device is operating in a standby state. The configuration registers (BCR and RCR) can be programmed and read using two methods: The CR Controlled Method (or Hardware Method) The Software Method. Programming and Reading the Configuration Registers using the CR Controlled Method The BCR and the RCR can be programmed and read using either a Synchronous or an Asynchronous Write and Read operation with the Configuration Register Enable input, CR, at VIH. Address bit A19 selects the register to be programmed or read (see Table 4., Register Selection). The values placed on address lines A0 to A21 are latched into the register on the rising edge of L, E, or W, whichever occurs first. LB and UB are "don't care". When CR is at VIL, a Read or Write operation will access the memory array. See Figures 27 and 33, Configuration Register Write in Asynchronous and Synchronous Modes. Table 4. Register Selection
Register RCR BCR Read or Write Operation Read/Write Read/Write A19 0 1
Programming and Reading the Configuration Registers by the Software Method Each register can be read by issuing a Read Configuration Register sequence (see Figure 9., Read Configuration Register (Software Method), and programmed by issuing a Set Configuration Register sequence (see Figure 8., Set Configuration Register (Software Method). Both sequences must be issued in asynchronous mode. The timings will be identical to those described in Table 15., Asynchronous Read AC Characteristics. The Chip Enable input, CR, is `don't care'. Read Configuration Register and Set Configuration Register sequences both require 4 cycles: 2 bus read and one bus write cycles to a unique address location, 3FFFFFh, indicate that the next operation will read or write to a configuration register. The data written during the third cycle must be `0000h' to access the RCR and `0001h' to access the BCR during the next cycle. The fourth cycle reads from or writes to the configuration register.
13/48
M69KB096AA
Figure 8. Set Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
E tEHEL2 G tEHEL2 tEHEL2
(4)
W
LB, UB
DQ0-DQ15
Don't Care
Don't Care
(2)
CR Data IN
AI10600b
Note: 1. 2. 3. 4.
Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to `0001h' and `000h' respectively. The highest order address location is not modified during this operation. The third write operation must be controlled by the Chip Enable signal.
Figure 9. Read Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
E tEHEL2 G tEHEL2 tEHEL2
(3)
W
LB, UB
DQ0-DQ15
Don't Care
Don't Care
(1)
CR Data OUT
AI10601b
Note: 1. 2. 3. 4.
To read the BCR, RCR on last bus read cycle, DQ0-DQ15 must be set to `0001h', `000h' respectively. The highest order address location is not modified during this operation. The Chip Enable signal, E, must be held High for 150ns before reading the content of the Configuration Register. The third write operation must be controlled by the Chip Enable signal.
14/48
M69KB096AA
Bus Configuration Register The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system memory bus. Overall, it is identical to its counterpart on burst mode Flash devices. At power-up, BCR is initialized to 9D4Fh. Refer to Table 5. for the description of the Bus Configuration Register Bits. Operating Mode Bit (BCR15). The Operating Mode bit allows the Synchronous Burst mode or the Asynchronous mode (default setting) to be selected. Latency Counter Bits (BCR13-BCR11). The Latency Counter bits are used to set the number of clock cycles between the beginning of a Read or Write operation and the first data becoming available. For correct operation, the number of clock cycles can only be equal to 3 or 4 (default settings) and the Latency Counter bits can only assume the values shown in Table 5., Bus Configuration Register Definition. See also Table 7., Latency Counter Configuration, and Figure 12., Example of Latency Counter Configuration). WAIT Polarity Bit (BCR10). The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a consequence, it also determines whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. By default, the WAIT output signal is active High. WAIT Configuration Bit (BCR8). The system memory controller uses the WAIT signal to control data transfer during Synchronous Burst Read Read and Write operations. The WAIT Configuration bit is used to determine when the transition of the WAIT output signal between the asserted and the deasserted state occurs with respect to valid data available on the data bus. When the Wait Configuration bit is set to `0', data is valid or invalid on the first Clock rising edge immediately after the WAIT signal transition to the deasserted or asserted state. When the Wait Configuration bit is set to `1' (default settings), the WAIT signal transition occurs one clock cycle prior to the data bus going valid or invalid. See Figure 10., WAIT Configuration Example, and Figure 11., Example of WAIT Configuration During Synchronous Burst Operation. Clock Configuration Bit (BCR6). The Clock Configuration bit is used to configure the activeedge of the Clock signal, K, during Synchronous Burst Read or Write operations. When the Clock Configuration bit is set to '1' (default setting), the rising edge of the Clock is active. Configuring the active clock edge to the falling edge (BCR6 set to `0') is not supported. All of the waveforms shown in this datasheet correspond to a Clock signal active on the rising edge. Driver Strength Bit (BCR5). The Driver Strength bit allows to set the output drive strength to adjust to different data bus loading. Normal driver strength (full drive) and reduced driver strength (a quarter drive) are available. By default, outputs are configured at `half drive" strength. Burst Wrap Bit (BCR3). The burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or allowed to step across the boundary (no wrap). The Burst Wrap bit is used to select between `wrap' and `no wrap'. If the Burst Wrap bit is set to `1' (no wrap), the device outputs data sequentially regardless of burst boundaries. When Continuous Burst operation is selected, the internal address switches to 000000h if the read address passes the last address. By default, Burst wrap is selected. See also Table 6., Burst Type Definition.
15/48
M69KB096AA
Burst Length Bits (BCR2-BCR0). The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation. They can be set for 4 Words, 8 Words, 16 Words or Table 5. Bus Configuration Register Definition
Address Bits A21-A20 A19 A18-A16 A15 A14 Bus Configuration Register Bit BCR15 BCR13BCR11 Description Register Select 1 Operating Mode Bit Latency Counter Bits (LC) Bus Configuration Register Selected Must be set to `0' Reserved 0 1 Synchronous Burst mode Asynchronous mode (default) Value Must be set to `0' Reserved 0 Refresh Selected Description
Continuous Burst (default settings), where all the Words are read sequentially regardless of address boundaries. Burst Write operations are always performed using the Continuous Burst mode.
Must be set to `0' Reserved 010 LC = 2 (3 Clock Cycles) LC= 3 (4 Clock Cycles) (default)
A13-A11
011
Other configurations reserved 0 A10 A9 BCR10 WAIT Polarity Bit 1 Wait Configuration Bit Clock Configuration Bit Driver Strength Bit Burst Wrap Bit 1 001 010 A2-A0 BCR2-BCR0 Burst Length Bit 011 111 16 Words Continuous Burst (default) No Wrap 4 Words 8 Words WAIT Active High (default) Must be set to `0' Reserved 0 A8 BCR8 1 WAIT Asserted During Delay WAIT Asserted One Clock Cycle Before Delay (Default) WAIT Active Low
A7 A6
BCR6
Must be set to `0' Reserved 0 1 0 1 Not supported Rising Clock Edge (Default) Full Drive (default) 1/4 Drive
A5 A4 A3
BCR5 BCR3
Must be set to `0' Reserved 0 Wrap (default)
Note: All Burst Write operations are performed in Synchronous Continuous Burst mode.
16/48
M69KB096AA
Table 6. Burst Type Definition
Mode Start 4 Words Add (Sequential) 0 1 2 Wrap (BCR3='0') 3 4 5 6 7 ... 14 15 0 1 2 No Wrap (BCR3='1') 3 4 5 6 7 ... 14 15 ... 14-15-16-17-18-19...-23-24-25-26-27-28-29 15-16-17-18-19-20...-24-25-26-27-28-29-30 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 ... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words (Sequential) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... 16 Words (Sequential) 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20... 15-16-17-18-19-20-21...
6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 7-8-9-10-11-12-1314 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22
Table 7. Latency Counter Configuration
Maximum Input Clock Frequency Latency Configuration Code 2 (3 Clock Cycles) 3 (4 Clock Cycles) Access Time 70ns Maximum Clock Rate in Burst Mode 80MHz 53 (18.75ns) 80 (12.5ns) Maximum Clock Rate in Burst Mode 66MHz 44 (22.7ns)(1) 66 (15.2ns) Unit
MHz MHz
Note: 1. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
17/48
M69KB096AA
Figure 10. WAIT Configuration Example
K
WAIT DQ0-DQ15 BCR8='0' Data Valid During Current Cycle DQ0-DQ15 BCR8='1' Data Valid During Next Cycle Hi-Z
Data[0] Data[1]
Hi-Z
Data[0]
AI06795
Figure 11. Example of WAIT Configuration During Synchronous Burst Operation
K WAIT BCR8='0' Data Valid During Current Cycle WAIT BCR8='1' Data Valid During Next Cycle DQ0-DQ15 Hi-Z Data[0] Data[1] Data[2] Data[3] Data[4]
AI06797
Figure 12. Example of Latency Counter Configuration
K
ADDRESS VALID
A0-A21
L 3 Clock Cycle Latency DQ0-DQ15 BCR13-BCR11='010' 4 Clock Cycle Latency DQ0-DQ15 BCR13-BCR11='011'
VALID OUTPUT VALID OUTPUT VALID OUTPUT AI08900 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
18/48
M69KB096AA
Refresh Configuration Register The Refresh Configuration Register (RCR) is used for two purposes: to define how the self refresh of the PSRAM array is performed to enable Page Read operations. Altering the self refresh parameters can dramatically reduce current consumption in Standby mode. At power-up, RCR is initialized to 0070h. Refer to Table 9. for the description of the Refresh Configuration Register Bits. Page Mode Operation Bit (RCR7). The Page Mode operation bit determines whether the Asynchronous Page Read mode is enabled. At powerup, the RCR7 bit is set to `0', and so the Asynchronous Page Read mode is disabled. Temperature Compensated Refresh Bits (RCR6-RCR5). The Temperature Compensated Refresh bits allow an adequate refresh rate to be selected at one of four different temperature thresholds: +15C, +45C, +70C, and +85C. The default setting is +85C. See the Temperature Compensated Refresh section for more details. Deep Power-Down Bit (RCR4). The Deep Power-Down bit enables or disables all refresh-related operations. The Deep Power-Down mode is enabled when the RCR4 bit is set to `0', and remains enabled until this bit is set to `1'. At power-up, the Deep Power-Down mode is disabled. See the Deep Power-Down section for more details. Partial Array Refresh Bits (RCR2-RCR0). The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total PSRAM array. The refresh options can be full array, one eighth, one quarter, one half, or none of the array. These memory areas can be located either at the top or bottom of the memory array. By default, the full memory array is refreshed (see Table 8., Address Patterns for Partial Array Refresh).
Table 8. Address Patterns for Partial Array Refresh
RCR2 RCR1 RCR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Refreshed Area Full Array (Default) Bottom Half of the Array Bottom First Quarter of the Array Bottom First Eighth of the Array None of the Array Top Half of the Array Top Quarter of the Array Top One-Eighth of the Array Address Space Size of Refreshe d Area Density
000000h-3FFFFFh 4 Mbitsx16 64 Mbits 000000h-1FFFFFh 2 Mbitsx16 32 Mbits 000000h-0FFFFFh 1 Mbitsx16 16 Mbits 000000h-07FFFFh 0 512Kbitsx 16 0 8 Mbits 0
200000h-3FFFFFh 2 Mbitsx16 32 Mbits 300000h-3FFFFFh 1 Mbitsx16 16 Mbits 380000h-3FFFFFh 512Kbitsx 16 8 Mbits
Note: RCR4 is set to `1'.
19/48
M69KB096AA
Table 9. Refresh Configuration Register Definition
Address Bits A21-A20 A19 A18-A8 A7 Bus Configuration Register Bit RCR7 Description Register Select 1 Page Mode Operation Bit Bus Configuration Register Selected Must be set to `0' Reserved 0 1 11 A6-A5 RCR6-RCR5 Temperature Compensated Refresh Bits 00 01 10 A4 A3 RCR4 Deep PowerDown Bit 0 1 Page Read Mode Disabled (Default) Page Read Mode Enabled +85C (Default) +70C +45C +15C Deep Power-Down Enabled Deep Power-Down Disabled (Default) Value Must be set to `0' Reserved 0 Refresh Selected Description
Must be set to `0' Reserved 000 001 010
A2-A0
RCR2-RCR0
Partial Array Refresh Bits
011 100 101 110 111
See Table 8., Address Patterns for Partial Array Refresh
20/48
M69KB096AA
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 10. Absolute Maximum Ratings
Symbol TA TSTG VCC VCCQ VIO Parameter Ambient Operating Temperature Storage Temperature Core Supply Voltage Input/Output Buffer Supply Voltage Input or Output Voltage Min -30 -55 -0.2 -0.2 -0.5 Max 85 150 2.45 4.0 4.0 or VCCQ+0.3
(1)
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C V V V
Note: 1. Whichever is the lower.
21/48
M69KB096AA
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 11., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 11. Operating and AC Measurement Conditions
M69KB096AA Parameter Min VCC Supply Voltage VCCQ Input/Output Buffer Supply Voltage Ambient Operating Temperature Load Capacitance (CL) VCCQ = 1.8V Output Circuit Protection Resistance (R1, R2) VCCQ = 2.5V VCCQ = 3.0V Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages Input Rise and Fall Time (t )
Note: 1. All voltages are referenced to VSS.
Unit Max 1.95 3.3 85 V V C pF k k k VCC V V V ns
1.7 1.7
-30
30 2.7 3.7 4.5 0 VCC/2
VRL = 0.3VCC; VRH = 0.7VCC 1.6
Figure 13. AC Measurement I/O Waveform
Figure 14. AC Measurement Load Circuit
VCCQ
I/O Timing Reference Voltage VCC VCC/2 0V
R1
DEVICE UNDER TEST CL
0.7VCC 0.3VCC
AI04831
OUT R2
Output Timing Reference Voltage VCC
0V
AI07222d
Note: 1. Logic states `1' and `0' correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at VCCQ/2 and output timings end at VCCQ/2. Input rise and fall time (10% to 90%) are lower than 1.6ns. 2. All the tests are performed with the outputs configured as Full drive strength (BCR[5]=0).
22/48
M69KB096AA
Table 12. Capacitance
Symbol CIN1 CIO Parameter Address Input Capacitance Data Input/Output Capacitance Test Condition VIN = 0V VIO = 0V Min Max 6 6 Unit pF pF
Note: 1. These parameters are not fully tested.
Table 13. DC Characteristics
Symbol ICC1 (1) Parameter Operating Current: Asynchronous Random Read/Write Operating Current: Asynchronous Page Read Operating Current: Initial Access, Burst Read/Write Operating Current: Continuous Burst Read Operating Current: Continuous Burst Write VCC Standby Current Input Leakage Current Output Leakage Current Deep-Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = -0.2mA IOL = 0.2mA VIN = VCCQ or 0V, E = VIH 0V VIN VCC G = VIH or E = VIH VIN = VIH or VIL 1.4 10 VCCQ + 0.2 0.4 VIN =VIH or VIL, E = VIL, IOUT = 0mA Test Condition 70ns 85ns 70ns 85ns 80MHz 66MHz 80MHz 66MHz 80MHz 66MHz Min. Typ Max. 25 20 15 12 35 30 18 15 35 30 120 1 1 Unit mA mA mA mA mA mA mA mA mA mA A A A A V V V 0.2VCCQ V
ICC1P (1)
ICC2 (1)
ICC3R(1) ICC3W(1) ISB(2) ILI ILO IZZ(3) VIH VIL VOH VOL
-0.2
0.8VCCQ
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive the output capacitance expected in the actual system. 2. ISB(Max) values are measured with RCR2 to RCR0 bits set to `000' (full array refresh) and RCR6 to RCR5 bits set to `11' (temperature compensated refresh threshold at +85C). In order to achieve low standby current, all inputs must be driven either to VCCQ or VSS. ISB may be slightly higher for up to 500 ms after power-up or when entering Standby mode. 3. The Operating Temperature is +25C.
23/48
M69KB096AA
Table 14. PAR and TCSR Specifications and Conditions
Symbol Parameter Test Condition Maximum Operating Temperature(2) Refreshed Unit Memory +15C +45C +70C +85C Areas RCR[6-5]=10 RCR[6-5]=01 RCR[6-5]=00 RCR[6-5]=11 Full Maximum VIN = VIH or Standby Current VIL, in TCSR and E = VIH PAR Modes 1/2 1/4 1/8 0 70 65 60 57 50 85 80 75 70 55 105 100 95 90 60 120 115 110 105 70 A
ISB
(1)
Note: 1. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB may be slightly higher for up to 500 ms after power-up or when entering Standby mode. 2. RCR values for 85C are 100 percent tested. TCR values for 15C, 45C and 70C are sampled only.
Figure 15. Asynchronous Random Read AC Waveforms
tAVAX A0-A21 VALID ADDRESS tAVQV L tEHEL E tELQV LB/UB tBLQV G tGLQV W Hi-Z tGLQX tBLQX
VALID OUTPUT
tEHQZ
tBHQZ
tGHQZ
tGHQX
DQ0-DQ15
Hi-Z
tELQX tELTV WAIT Hi-Z
tEHTZ Hi-Z
AI06780b
24/48
M69KB096AA
Figure 16. L Controlled Asynchronous Random Read AC Waveforms
A0-A21
VALID ADDRESS
tAVQV tAVLH tLHLL L tLLQV tLLLH tEHEL E tELQV LB/UB tBLQV G tGLQV W Hi-Z tGLQX tBLQX
VALID OUTPUT
tLHAX
tELLH
tEHQZ
tBHQZ
tGHQZ
tGHQX
DQ0-DQ15
Hi-Z
tELQX tELTV WAIT Hi-Z
tEHTZ Hi-Z
AI06781b
25/48
M69KB096AA
Figure 17. Asynchronous Page Read AC Waveforms
tAVAX A4-A21 VALID ADDRESS
A1-A3 tAVQV L
VALID ADDRESS
VALID
VALID tAVAV
VALID
tEHEL tEHEL E tELQV LB/UB tBLQV G tGLQV W tGLQX tBLQX DQ0-DQ15 Hi-Z tELQX WAIT Hi-Z tELTV tEHTZ Hi-Z
AI06782b
tEHQZ
tBHQZ
tGHQZ
tGHQX
tAVQV1 tAVQX
VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
Hi-Z
26/48
M69KB096AA
Table 15. Asynchronous Read AC Characteristics
M69KB096AA Symbol Alt. Parameter Min tAVQV tLLQV tAVQV1 tLHAX tAVLH tBLQV tBHQZ(4) tBLQX(3) tEHEL tELEH(2) tELTV tEHTZ tELQV tELLH tEHQZ(4) tELQX(3) tGLQV tGHQX tAVQX tGHQZ(4) tGLQX(3) tAVAV tAVAX tLLLH tLHLL tCO tCVS tHZ tLZ tOE tOH tOHA tOHZ tOLZ tPC tRC tVP tVPH tAA tAADV tAPA tAVH tAVS tBA tBHZ tBLZ tCBPH tCEM tCEW Address Valid to Output Valid L Low to Output Valid Page Access Time L High to Address Transition Address Valid to L High Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable High to Output HiZ Upper/Lower Byte Enable Low to Output Transition Chip Enable High between Subsequent Mixed-Mode Read Operations Maximum Chip Enable Pulse Width Chip Enable Low to WAIT Valid Chip Enable high to WAIT High-Z Chip Enable Low to Output Valid (Chip Select Access Time) Chip Enable Low to L High Chip Enable High to Output Hi-Z Chip Enable Low to Output Transition Output Enable Low to Output Valid Output Enable High to Output Transition Data Hold from Address Change Output Enable High to Output Hi-Z Output Enable Low to Output Transition Page Cycle Time Read Cycle Time L Pulse Width Low L Pulse Width High 5 20 70 10 10 5 5 8 5 25 85 10 10 ns ns ns 10 20 5 5 8 10 8 10 20 1 10 5 8 7.5 8 70 10 8 1 5 10 70 8 10 5 8 7.5 8 85 70ns Max 70 70 20 5 10 85 8 ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns Min 85ns Max 85 85 25 ns ns ns Unit
Note: 1. All the tests are performed with the outputs configured in "Full drive" strength (BCR5='0'). 2. The timing is related to Asynchronous Page mode only. 3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a transition of 100mV between the High-Z level (VCCQ/2) and VOH or VOL. 4. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a transition of 100mV between VOH or VOL and VCCQ/2.
27/48
M69KB096AA
Figure 18. Single Access Synchronous Burst Read AC Waveforms
tKHKH K tAVKH tKHAX A0-A21 ADDRESS VALID tAVLH L tLLKH tELKH E tGLQV G tWHKH tKHWX tGLQX tGHQZ tKHLH tKHQV1 tKHEH tEHQZ tKHKL
W
tBLKH LB/UB Hi Z
tKHBX
tELTV
tKHTV Hi Z tKHQV2 tKHQX2 Hi-Z
WAIT
DQ0-DQ15
Hi-Z Burst Read Identified (W = High)
VALID OUTPUT
AI06783
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
28/48
M69KB096AA
Figure 19. Synchronous Burst Read (4-word) AC Waveforms
tKHKH K tAVKH A0-A21 tAVLH tLLKH
VALID ADDRESS
tKHKL
tKHAX
tKHLH
tKHEH tEHEL
L
tELKH tKHQV1
E
tGLQV tEHQZ
G
tWHKH tKHWX tGLQX tGHQZ
W
tBLKH tKHBX
LB/UB
tELTV WAIT D0-D15 Hi-Z tKHQZ Hi-Z tKHQX2
VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
tKHTX Hi-Z
READ Burst Identified (W = High)
AI06784
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
29/48
M69KB096AA
Figure 20. LB/UB Controlled, Synchronous Burst Read (4-word) AC Waveforms
tKHKH tKHKL
K tAVKH A0-A21 tAVLH tLLKH tKHLH tKHEH
VALID ADDRESS
tKHAX
L
tELKH tKHQV1
tEHEL
E
tGLQV tEHQZ
G
tWHKH tKHWX tGLQX tGHQZ
W
tBLKH tKHBX
LB/UB
tELTV WAIT DQ0-DQ15 Hi-Z tKHQZ Hi-Z tKHQX2
VALID OUTPUT
tKHTX Hi-Z tKHQZ tKHQX1 Hi-Z
VALID OUTPUT
tKHQZ
VALID OUTPUT
READ Burst Identified (W = High)
AI06785
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. The Burst Length bits BCR0 to BR2 are set to `001' (4 Words). 3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
30/48
M69KB096AA
Figure 21. Synchronous Burst Read Suspend and Resume Waveforms
tKLKL tKHKL
tAVKH 0-A21 tAVLH Valid Address
tKHAX Valid Address tLLKH tKH
L
tLLKH tELKH tKHLH tEHQZ tEHEL
tGHQZ
tGLQV
tGHQZ
tWHKH
tKHWX
tGLQX
W
tBLKH tKHBX tGLQX
B/UB
tGLQV WAIT Hi-Z Hi-Z
0-D15
Hi-Z tKHQV1
Valid Output
Valid Output tKHQX2
Valid Output
Valid Output
Valid Output
Valid Output
AI08760c
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
31/48
M69KB096AA
Figure 22. Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)
tKLKH K tKHKH A0-A21 tF DON'T CARE DON'T CARE
L
LB/UB
E
(4)
G
W
DON'T CARE tKHTV tKHTX (3) VALID OUTPUT VALID OUTPUT tKHQV2 WAIT CONFIGIGURED WITH BCR8 = '0' WAIT CONFIGIGURED WITH BCR8 = '1'
DON'T CARE
WAIT DQ0-DQ15
VALID OUTPUT
VALID OUTPUT tKHQX2
AI06787b
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, WAIT asserted during delay; Burst Wrap bit BCR3 set to `0' (wrap). 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. 3. WAIT will be asserted for a maximum of 2xLC Cycles (LC being the Latency code set through BCR[13-11]). 4. E must not remain Low longer that tELEH.
32/48
M69KB096AA
Table 16. Synchronous Burst Read AC Characteristics
M69KB096AA Symbol Alt. Parameter 80MHz Min tKHQV1 tKHQV2 tAVLH tGLQV tEHEL(5) tELTV tELEH
(5)
66MHz Min Max 56 11 10
Unit
Max 46.5 9
tABA tACLK tAVS tBOE tCBPH tCEW tCEM tCLK tCSP
Burst Access Time Delay From Clock High to Output Valid Address Valid to L High Delay From Output Enable Low to Output Valid in Burst mode Chip Enable High between Subsequent Mixed-Mode Read Operations Chip Enable Low to WAIT Valid Maximum Chip Enable Low Pulse Clock Period Chip Enable Low to Clock High 12.5 4.5 5 1 10
ns ns ns
20 5 7.5 8 20 20 15 5 1
20
ns ns
7.5 8 20 20
ns ns ns ns
tKHKH(4) tELKH tKHAX tKHBX tKHWX tKHEH tKHLH tEHQZ(2) tR tF tKHTV tKHTX tKHQZ tKHQX1 tKHQX2 tKHKL tKLKH tGHQZ(2) tGLQX(3) tAVKH tLLKH tBLKH tWHKH tCHKH
tHD
Hold Time From Active Clock Edge
2
2
ns
tHZ tKHKL tKHTL tKHZ tKLZ tKOH tKP tOHZ tOLZ
Chip Enable High to Output Hi-Z Clock Rise Time Clock Fall Time Clock High to WAIT Valid Clock High to WAIT Transition Clock High to Output Hi-Z Clock High to Output Transition Output Hold from Clock High Clock High to Clock Low Clock Low to Clock High Output Enable High to Output Hi-Z Output Enable Low to Output Transition 5 3 2 2 4
8 1.8 9 8 5 3 2 2 5 8 5
8 2.0 11 8 5
ns ns ns ns ns ns ns
8
ns ns
tSP
Set-up Time to Active Clock Edge
3
3
ns
Note: 1. All the tests are performed with the outputs configured in "Full drive" strength (BCR5='0'). 2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a transition of 100mV between VOH or VOL and VCCQ/2. 3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a transition of 100mV between the High-Z level (VCCQ/2) and VOH or VOL. 4. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. 5. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
33/48
M69KB096AA
Figure 23. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX A0-A21
VALID ADDRESS
tAVWH L tAVEL E tBLBH LB/UB tELEH, tELWH
tWHAX
G tWHWL W tDVEH tEHDX DQ0-DQ15 Hi-Z tELTV WAIT Hi-Z
VALID INPUT
tWLWH
tEHTZ Hi-Z
AI06788c
Figure 24. LB/UB Controlled, Asynchronous Write AC Waveforms
tAVAX A0-A21
VALID ADDRESS
tAVWH L tELEH, tELWH
tWHAX
E tBLBH
LB/UB
G tWHWL W tDVEH Hi-Z tELTV WAIT Hi-Z
VALID INPUT
tWLWH
DQ0-DQ15
tEHDX
tBHTZ Hi-Z
AI06789d
34/48
M69KB096AA
Figure 25. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX A0-A21
VALID ADDRESS
tAVWH L tELEH, tELWH E tBLBH LB/UB
tWHAX
G tWHWL W tAVWL DQ0-DQ15 Hi-Z tELTV WAIT Hi-Z tDVEH
VALID INPUT
tWLWH
tEHDX
tWHTZ Hi-Z
AI06790c
35/48
M69KB096AA
Figure 26. L Controlled, Asynchronous Write AC Waveforms
A0-A21 tAVLH tLLWH tLHLL L tAVWH tELEH, tELWH E tBLBH LB/UB tLLLH
VALID ADDRESS
tLHAX
G tWLWH W tDVEH DQ0-DQ15 Hi-Z tELTV WAIT Hi-Z
VALID INPUT
tWHWL
tEHDX
tWHTZ Hi-Z
AI06791c
36/48
M69KB096AA
Figure 27. Configuration Register Write in Asynchronous Mode Followed by Read Operation
K A0-A21 except A19 ADDRESS
OPCODE tAVLH Select Control Register
A19
ADDRESS
CR tLHLL L
tAVLH
tLLVH Initiate Control Register Access tELWH
tEHEL
E
G
tWLWH Write Address Bus Value to Control Register
W
LB/UB DATA VALID
DQ0-DQ15
AI06778
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during delay. 2. A19 = VIL to load RCR; A19 = VIH to load BCR.
37/48
M69KB096AA
Figure 28. Asynchronous Write Followed by Synchronous Burst Read (4-word) AC Waveforms
tGHQZ Hi-Z
AI11317 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
tKHKL
tKHKH
tGLQV
tKHQV1
tKHAX
VALID ADDRESS
tKHLH
tKHWX
tWHAX
tELKH
tWHKH
tBLKH
tKHBX
tAVKH
tLLKH
tELTV
tEHEL
VALID ADDRESS
tAVAX
tLHAX
tLLWH
tLLWL
tWLWH
tWHWL
VALID ADDRESS
tAVAX
tAVWH
tBLWH
tAVWL
tAVLH
tLHLL
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns. 3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
38/48
D0-D15
A0-A21
LB/UB
WAIT
W
G
K
L
E
tWLDV Hi-Z
tELWH
tLLLH
tBLLH
tWHDX
tDVWH
(2)
tKHQZ
tKHQX2
M69KB096AA
Figure 29. Synchronous Burst Read (4-word) Followed by Asynchronous Write AC Waveforms
tWHWL
AI11318 VALID OUTPUT VALID INPUT
tLHAX
VALID ADDRESS
tELEH, tELWH
tWLWH
tAVLH
tWHTZ
tLLLH
tLLWH
tELWL
tEHQZ
tAVWL
tBLBH
(1) tEHEL
tELTV
tGHQZ
tKHEH
tKHTV
tLHLL
tGLQV
tKHKH
tKHAX
tKHLH
tKHQV1
tKHWX
tGLQX
tKHBX
tELTV
tKHQV2
tKHQX2
tDVEH
tEHDX
Hi-Z
tWHKH
tLLKH
tELKH
tBLKH
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
K
DQ0-DQ15
A0-A21
LB/UB
WAIT
E
W
L
G
Hi-Z
Hi Z
Burst Read Identified (W = High)
tAVKH
ADDRESS VALID
39/48
M69KB096AA
Table 17. Asynchronous Write AC Characteristics
M69KB096AA Symbol Alt. Parameter 70ns Min tAVEL tAVWL tAVBL tLLWL tELWL tLHAX tAVLH tAVWH tAVBH tBLBH tBLEH tBLWH tELTV tAXCH Max 85ns Min Max Unit
tAS
Address Setting Time
0
0
s
tAVH tAVS tAW
L High to Address Transition Address Valid to L High Address Valid to Write Enable High Address Valid to Upper/Lower Byte Enable Transition Upper/Lower Byte Enable Low to End of Write Operation Chip Enable Low to WAIT Valid In Mixed-Mode Operation: Delay between Address Transition in Asynchronous Write mode and Clock High in Burst Read mode Chip Enable High between Subsequent Asynchronous Operations Chip Enable Low to L High Chip Enable Low to End of Write Operation
5 10 70
5 10 85
ns ns ns
tBW tCEW tCKA
70 1 70 7.5
85 1 85 7.5
ns ns ns
tEHEL tELLH tBLLH tELBH tELWH tEHDX tWHDX tBHDX tDVEH tDVBH tDVWH tLLLH tLHLL tLLWH tAVAX tWHWH tWLBH tWLEH tWLWH tWHWL tWHAX tWLDV
tCPH tCVS tCW
5 10 70
5 10 85
ns ns ns
tDH
Input Hold from End of Write Operation
0
0
ns
tDW tVP tVPH tVS tWC
Data to Write Time Overlap L Pulse Width Low L Pulse Width High L Low to Write Enable High Write Cycle Time
23 10 10 70 70
23 10 10 85 85
ns ns ns ns ns
tWP tWPH tWR tWHZ
Write Pulse Width Write Enable Pulse Width High Write Enable High to Address Transition Write Enable Low to Data Valid
46 10 0 8
55 10 0 8
ns ns ns ns
40/48
M69KB096AA
M69KB096AA Symbol Alt. Parameter 70ns Min tAVEL tAVWL tAVBL tLLWL tELWL tLHAX tEHTZ tBHTZ tWHTZ Max 85ns Min Max Unit
tAS
Address Setting Time
0
0
s
tAVH tHZ
L High to Address Transition Chip Enable High to WAIT Hi-Z LB/UB High to WAIT Hi-Z Write Enable High to WAIT Hi-Z
5 8
5 8
ns ns
Note: 1. WE# LOW time must be limited to tCEM (8 s). 2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The transition timings measure a transition of 100 mV between the High-Z level (VCCQ/2) and VOH or VOL. 3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The High-Z timings measure a transition of 100 mV between VOH or VOL and VCCQ/2.
Figure 30. Synchronous Burst Write AC Waveform
tKHKH
K
A0-A21
VALID ADDRESS
tAVKH tLLKH L tBLKH LB/UB tELKH tKHEH tELEH tEHEL tKHBH tKHLH
E
G
tWHKH
tKHWH
W tELTV WAIT Hi-Z tDVKH tKHDX Hi-Z WRITE Burst Identified (W = Low)
AI06792b
VALID INPUT VALID INPUT VALID INPUT VALID INPUT
tKHTV Hi-Z
D0-D15
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; WAIT asserted during delay. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
41/48
M69KB096AA
Figure 31. Continuous Burst Write Showing an Output Delay for End-of-R ow Condition (BCR8=0)
tKLKH K tKHKH A0-A21 tF DON'T CARE DON'T CARE
L
LB/UB
E
G
W
DON'T CARE tKHTV tKHTX (3)
tDVKH tKHDX
DON'T CARE
WAIT
DQ0-DQ15
VALID INPUT D[n]
VALID INPUT D[n+1]
VALID INPUT D[n+2]
VALID INPUT D[n+3]
VALID INPUT D[n+4]
End of Row
AI06793b
Note: 1. 2. 3. 4.
Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, Burst Wrap bit BCR3 set to `0' (wrap). Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. WAIT will be asserted for a maximum of (2xLC)+1 cycles (LC being the Latency Code set through BCR[13-11]) Taking E high or L Low will abort the Burst operation and the writing of the first data.
42/48
M69KB096AA
Figure 32. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
tKHKH K tKHAX tAVKH Addr. tKHLH tLLKH L tELKH E tKHEH tKHLL tKHKL
tKLKH
tKHAX tAVKH
tKHLH
tEHEL (2) tELKH
tKHEH
tGLQX
tGHQZ
G tWLKH W tKHWH UB, LB tKHTX WAIT tDVKH DQ0DQ15
DIN0
tWHKH
tKHWL
tKHTX
tKHDX
DIN1 DIN2 DIN3 DO0 DO1 DO2
tKHQX2
DO3
ai11313
Note: 1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). In fixed Latency mode, row boundary crossing 2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH.
43/48
M69KB096AA
Figure 33. Configuration Register Write in Synchronous Mode Followed by Read Operation
K Latch Control Register Value A0-A21 except A19 tAVKH A19 tRHKH CR tCHKH L tEHEL tELKH E tKHLH tKHRL
OPCODE ADDRESS
Latch Control Register Address
ADDRESS
G tWLKH W tKHLH
LB/UB tELTV Hi-Z Hi-Z
WAIT
DQ0-DQ15
AI06779b
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during delay. 2. A19 = VIL to load RCR; A19 = VIH to load BCR.
44/48
M69KB096AA
Table 18. Synchronous Burst Write AC Characteristics
M69KB096AA Symbol Alt. Parameter 80MHz Min tEHEL(1) tELTV tKHKH
(2)
66MHz Min 5 Max
Unit
Max
tCBPH tCEW tCLK tCSP
Chip Enable High between Subsequent Mixed-Mode Read Operations Chip Enable Low to WAIT Valid Clock Period Chip Enable Low to Clock High
5 1 12.5 4.5 7.5 20 20
ns 7.5 20 20 ns ns ns
1 15 5
tELKH tKHAX tKHBH tKHWH tKHEH tKHLH tKHRL tR tF tKHTV tKHKL tAVKH tBLKH tWHKH tWLKH tCHKH tRHKH tELEH(1)
tHD
Hold Time From Active Clock Edge
2
2
ns
tKHKL tKHTL tKP
Clock Rise Time Clock Fall Time Clock High to WAIT Valid Clock High to Clock Low 4
1.8 9 5
2.0 11
ns ns ns
tSP
Set-up Time to Active Clock Edge
3
3
ns
tCEM
Maximum Chip Enable Pulse Width
8
8
s
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns. 2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
Figure 34. Power-Up AC Waveforms
E
tVCHEL 1.7V Device Initialization Device Ready For Normal Operation
VCC, VCCQ
AI06794
Table 19. Power-Up AC Characteristics
M69KB096AA Symbol Alt. Parameter Min tVCHEL tPU Initialization delay 70ns Max 150 85ns Min Max 150 s Unit
45/48
M69KB096AA
PART NUMBERING
Table 20. Ordering Information Scheme
Example: Device Type M69 = PSRAM Mode K =Tested Die Operating Voltage B = VCC = 1.7 to 1.95V, Burst, Address/Data Bus Standard x16 Array Organization 096 = 64 Mbit (4Mb x16) Option A = 1 Chip Enable Die Revision A = Revision A Speed Class 70 = 70ns 85 = 85ns Maximum Clock Frequency A= 66 MHz Max Clock Frequency in Burst Read Mode C= 80MHz Max Clock Frequency in Burst Read Mode Package W = Unsawn Wafer Operating Temperature 8 = -30 to 85 C M69KB096 A A 70 C W 8
The notation used for the device number is as shown in Table 20.. Not all combinations are necessarily available. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
46/48
M69KB096AA
REVISION HISTORY
Table 21. Document Revision History
Date 13-Oct-2004 Rev. 0.1 First Issue. ISB current for Standard Leakage option added in FEATURES SUMMARY. ISB current for Standard Leakage option added in Table 13., DC Characteristics and test conditions updated. ITCR current for Standard Leakage option added in Table 14., Temperature Compensated Refresh Specifications and Conditions. IPAR current for Standard Leakage option added in Table 15., Partial Array Refresh Specifications and Conditions. Standard Leakage option added in Table 20., Ordering Information Scheme. Root Part Number changed to M69KB096AA. 104MHz maximum clock frequency and Low Leakage option removed. Temperature range updated to -30C to +85C. Clock Input (K). definition updated. Figure 3., Block Diagram modified. Bus Modes Tables 2, 3 and Synchronous Burst Mode paragraph updated. Output Impedance Bit (BCR5) renamed Driver Strength and definition updated. R1 and R2 updated in Table 13., DC Characteristics and Refresh Specifications and Conditions tables merged into Table 14.. Figures 15, 16, and 17 describing Asynchronous Read AC waveforms updated. Figures 18, 19, 20, 21 and 22 describing Synchronous Read AC waveforms updated. Figures 23, 24, and 25, describing Asynchronous Write AC waveforms updated. tAVWL and tAVBL added in Table 17., Asynchronous Write AC Characteristics. Figures 28 and 29 added. Figures 30, 31, and 32, describing Synchronous Write AC waveforms updated. Figure 32., Synchronous Burst Write Followed by Read AC Waveforms (4 Words) added. tRHKH and tKHRL added in Table 18., Synchronous Burst Write AC Characteristics Table 21., Bond Pad Location and Identification modified to express the pad coordinates from the center of the die. , FEATURES SUMMARY, OPERATING MODES and Figure 5., Synchronous Burst Write Mode (4-word burst) modified. Updated Note 2 in Table 13., page 23, added notes to Table 14., page 24 and Table 17., page 40. Deleted Note 5 from Table 15., page 27. Clock rate added in datasheet title. Test conditions for ICC1, ICC1P, ICC2, ICC3R, ICC3W and ISB updated in Table 13., DC Characteristics. Section Wafer and die specifications removed. Revision Details
11-Feb-2005
0.2
29-Apr-2005
1.0
16-June-2005 18-Aug-2005
2.0 3.0
12-Dec-2005 19-Jan-2006
4 5
47/48
M69KB096AA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
48/48

▲Up To Search▲

Price & Availability of M69KB096AA85AW8

	To Download M69KB096AA85AW8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .